Digital dynamic convergence control system in a display system.

专利摘要:

公开号:NL1019845A1
申请号:NL1019845
申请日:2002-01-28
公开日:2003-05-27
发明作者:Seung Won Seo；Hyo Seok Kwon；Young Hoon Jung；Ick Chan Shim
申请人:Samsung Electro Mech；
IPC主号:

专利说明:

Ly-LLctci-L ayiidiu-Löcn uunveiyeiu-ieDestUiinybbysceem in a weather-ive system
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a digital dynamic convergence error control system adapted for use in a deflection yoke of a display device and, more particularly, to a digital dynamic anvergence error control system that performs separate and independent correction error corrections in accordance with inspection intersections of a reference screen pattern gebieden respective areas between the intersections of the reference screen pattern.
Description of the related art
Generally, a deflection yoke performs a function of reflection of R, G, B electron beams that come down to a desired position of a screen at a CRT display device. Although the image quality of the screen must have a high definition solution, a conventional deflection yoke can achieve an improved convergence function for obtaining the high definition of the image quality. Various aortic auxiliary correction devices are therefore mounted in the deflection yoke for the convergence function for the high definition and the resolution of the display.
The yoke is provided with a dynamic convergence antroller mounted on a neck portion of the front yoke of a plurality of magnetic control coils for generating magnetic fields with one or two poles, magnetic fields with four poles and magnetic six-pan fields, using magnetism principles of consistency purity so that a G electron beam is moved to a desired position relative to R and B electron beams.
The dynamic convergence controller is needed to achieve the Dge resolution of the same image quality as a 3TV for processing a punctuation mark and transferring punctuation mark information in the presence of the digital TV broadcast.
Typically, the dynamic convergence controller of the conventional deflection yoke is provided with a number of resistors, inductors, capacitors, and diodes. The convergence error is compensated by controlling the current of the magnetic field control coils using adjustment means such as a variable resistor of the dynamic convergence control circuit.
With the conventional convergence controller, only a predetermined current wave is input to the magnetic control coils so that only a convergence error with a predetermined pattern is controlled. When a convergence error for a predetermined area of the screen is corrected, a different error is caused for the other area of the screen since the other convergence error of the other area varies in response to the convergence error for the predetermined area. It is therefore not advantageous that not all errors can be controlled over the entire screen.
When the convergence error detected manually in a manufacturing process of the deflection yoke and the CRT display device is controlled in accordance with the manual detection, it is impossible to control the convergence error of the entire screen of a flat and wide angle display device -CRT.
In an attempt to overcome the problems that arise with the manual adjustment of the convergence error with the manual detection of the user, a detection device adapted for use with an LCD display panel or a plasma display panel has been proposed for detecting and displaying convergence errors.
This detection device comprises a predetermined screen pattern where each color is applied to the screen of the detected CRT display device, an image detection device for detecting the screen pattern in each of the color components R, G and B (RGB) an image processor that processes the detected RGB components and a display panel that displays the results of processing by the image processor.
For example, Japanese Patent Publication 8-307898, published in 1996, discloses a convergence detection device that detects a predetermined white screen pattern displayed on a CRT using a camera provided with color detection sensors, such as a ccd (charged coupled device), with respective R and B component luminance centers are calculated from the screen pattern displayed on the CRT detected with respect to the white screen pattern and controlling the screen pattern with the relative displacements of the luminance centers that are considered convergence errors. This convergence detection device therefore calculates the light emission position of each color component on the screen pattern using the lumensance position in the screen pattern of each color component and calculates the relative displacements of the light emission positions of the respective color components.
This detection device has disadvantages in that the detected errors vary in response to moisture and temperature. The adjustment map illuminated by a lamp 104 shown in Fig. 1 is therefore needed before the convergent out is detected.
The adjustment card consists of a cross-line pattern 105 formed on a slightly impervious white plate. The adjustment map provided is detected on the image detection device 101 of the convergence detection device 100 and adjustment data for the relative position of each area color using the detected image. The calculated adjustment data is stored in a memory and is used to control the screen pattern with each color component.
In the conventional method of correcting the relative deviation of the area sensors, each position of the area sensors in the reference coordinate system of the convergence detection device is calculated using image data of all color components obtained from the detected adjustment map. Therefore, a longer period of time is needed to calculate the adjustment data as the parameters for the calculation increase. Moreover, it is impossible to control and adjust the convergence detection system during the manufacturing process since the specific additional adjustment map is used instead of a screen pattern that is moved on the CRT.
In another attempt to improve the aforementioned disadvantages, Korean Patent Publication 1999-013780 discloses an automatic convergence detection apparatus with a color CRT as shown in FIG. 2. FIG. 1 is a schematic diagram of the convergence detection device 1 provided with an image detection device 2 and an error detection device 3.
The image detection device 2 detects a predetermined detection pattern as such a screen pattern with horizontal and vertical cross lines or a dot pattern displayed on a display panel 4 being detected and includes a set of cameras 21, 22 for detecting a set of stereo images from the detection pattern. The error detection device 3 calculates the magnitude of the convergence using the stereo image data and displays the calculated convergence error on the display device 36.
The camera 21, 22 is provided with dichroic prisms 212 located near an image lens unit 211 to split a light beam into three color and component components, as well as image detection elements 213R, 213G, 213B including the CCD, in a position corresponding to each of the three color components emitted from the prism 212.
The cameras 21, 22 are provided with an image detection circuit 214 that controls the image detection elements (CCD) 213R, 213G, 213B, a focusing element 215 that automatically controls the focus of the image lens, and a signal processor 216 that processes image signals that are sent from the CCD 213R, 213G, 213B and generates the image signals to the image detection device 3,
The image detection circuitry 214, 224 is controlled by an image detection control signal generated from the image detection device 3 and the detection operation relating to the electron charge of the CCD 213R, 213G, 213B is controlled by the image detection control signals.
The focus control circuit 215, 225 is controlled by a focus control signal sent from the image detection device 3. A group of lenses 211A of the image lens unit 211 is therefore operated and an optical image of the screen pattern displayed on the CRT is converged on an image detection surface of the CCD 213R, 213G, 213B.
A focus control operation is performed by a focus signal from the controller 33. In the camera 21, the controller selects the high-frequency component of the green image (edge of the screen pattern) from the image detected by the CCD 213G and outputs the focus signal to the focus control circuit 215 so that the high frequency component is maximized to make the edge of the screen pattern clear.
The focus control circuit 215 shifts the set of lenses 211A in forward and backward directions to adjust the focusing of the image lens unit 211.
However, although the focus control operation is performed using the detected image as described above, the focus control operation is performed using a distance between the camera and a display surface of the color CRT, since the camera 21, 22 is provided with a sensor for detecting the distance.
The image detection device 3 is provided with analogue / digital (A / D) converters 3IA, 31B, image memory 32A, 32B, a controller 33, a data input device 34, a data output device 35 and a display device 36.
The A / D converters 31A, 31B convert an analog image signal into a digital input image signal. The image memories 32A, 32B store the digital input image signal generated by the A / D converters 31A, 31B.
Each of the A / D converters 31A, 31B is provided with three A / D converting circuits that correspond to the respective RGB components of the image signals. Each of the image memories 32A, 32B is provided with three frame memories corresponding to respective RGB components of the image signals.
The controller 33 is provided with a microcomputer, a ROM 331, and a RAM 32. The ROM 331 stores a program for processing a convergence error detection process, including an optical system drive process, image data calculation processes, etc. and stores data such as the convergence error correction data and the data conversion table. The RAM 332 is divided into a number of data areas and process areas for performing each step of the conversion error detection process.
The magnitude of the convergence error calculated in the controller 33 is stored in the RAM 332, displayed on a display device 36 in a predetermined format and also printed on an external device such as a printer or an external memory, via the data output device 35.
The data input device 34 includes a keyboard for inputting various data for the convergent outdetection process and inputting data for pitch distances between the pixels of the CCD 213, 223 and for detecting the dots of the display surface of the color CRT display - device 4.
The color CRT display device 4 to be detected includes a color CRT displaying an image, as well as a driver control circuit 42 that controls the operations of the color CRT.
A pattern generator 5 generates a video signal for the screen pattern. The video signal for the screen pattern is supplied to the control color circuit 42. The deflection circuit of the color CRT 41 is driven by the video signal and the screen pattern with horizontal and vertical cross lines is displayed on the color CRT 4.
In the convergence error detection device 1, the screen pattern is detected by two cameras 21, 22 of the image detection device 2 and the magnitude of the convergence error is calculated using the image data obtained from the cameras 21, 22.
FIG. 3 is a diagram showing a screen pattern 6 displayed on the color CRT 41. The screen pattern 6 comprises a plurality of vertical lines and horizontal lines that are perpendicular to the vertical lines. The screen pattern 6 with a number of intersections formed by the vertical lines and the horizontal lines is displayed on the display surface 41a of a color CRT. One of the detection areas A1 to An for detecting the magnitude of the convergence error comprises at least one intersection.
In each of the detection areas Ar (r = 1, 2, ... n), the magnitude of the horizontal convergence error DX in a direction X in an XY coordinate system is obtained from the image detection of the vertical lines located in the detection area Ar and the magnitude of the vertical convergence error DY in a direction Y in the DY coordinate system is obtained from the image of the horizontal lines present in the detection area Ar.
When the exact size of the convergence error is obtained from each, it is impossible to independently control each area with an independent convergence error in accordance with the respective independent area since the convergence error obtained from the screen pattern affects the entire area. Therefore, one area is corrected with the convergence error while the other area is not corrected with the convergence error.
When a portion of the convergence error is controlled, the other portion of the convergence varies since the convergence error controls the entire portions.
However, it is impossible to correct the respective convergence error with a high resolution HDTV.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved dynamic convergence control system that is capable of controlling magnetic fields of a deflection yoke with separate and independent convergence error correction data in accordance with respective pixels on a screen.
It is another object to provide an improved dynamic convergence control system that is capable of performing separate and independent convergence correction operations corresponding to each point of a horizontal and vertical reference pattern of a screen.
It is yet another object to provide an improved dynamic convergence control system that is capable of performing separate and independent convergence error correction operations corresponding to each area between intersections of horizontal and vertical reference patterns of a screen.
It is yet another object to provide a dynamic convergence control system capable of first adjusting separately and independently convergence error correction data corresponding to respective pixels in a first screen with a first screen size, to second separate and independent convergence error correction data corresponding to respective pixels on a second screen with a second screen size.
It is yet another object to provide a dynamic convergence control system that is capable of generating at least two separate and independent convergence error correction data for each field of an image frame.
It is also an object to provide a dynamic convergence control system that is capable of generating at least two separate and independent convergence error correction data corresponding to magnetic field control coils in each field of an image frame.
It is a further object to provide a dynamic convergence control system comprising eight convergence control coils capable of selectively generating two-pole magnetic fields, four-pole magnetic fields and six-pole magnetic fields.
It is a further object to provide a dynamic convergence control system capable of operating eight convergence control coils as two convergence correction coils for generating two magnetic fields with a horizontal axis or a vertical axis, four convergence correction coils for generating four-pole magnetic fields with a horizontal axis or a vertical axis and six convergence correction coils for generating six-pole magnetic fields.
It is a further object to provide a dynamic convergence control system that is capable of generating a number of variable convergence correction signals for a field of an image frame.
It is a further object to provide a dynamic convergence control system that is capable of generating a number of variable convergence control signals for each of the RGB deflection yokes of a display device.
It is a further object to provide a dynamic convergence error correction system that is capable of preventing all independent convergence error correction data corresponding to respective correction points of a screen from affecting other correction points when a specific point of the screen is corrected by the con License error correction data corresponding to the specific point.
It is a further object to provide a dynamic convergence error correction system capable of storing a number of convergence error correction data corresponding to intersections of a screen as well as a number of interpolation data corresponding to an area located between adjacent intersections of the screen.
It is a further object to provide a display device with a dynamic convergence error correction device that is capable of generating a number of independent convergence error correction data according to respective correction points located within a period of a horizontal synchronization signal.
It is a further object to provide a deflection yoke provided with a dynamic convergence error correction device capable of generating a number of independent convergence error correction data corresponding to respective correction points located within a period of a horizontal synchronization signal.
These and other objectives can be achieved by providing a digital dynamic convergence error control system for performing separate and independent convergence error correction operations according to each intersection of a horizontal and vertical reference pattern of a screen by receiving separate and independent correction data corresponding to respective intersections of the screen from an external device, storing the correction data in a memory, reading the correction data from the memory in response to an image scanning period other than a retrace period by using horizontal and vertical synchronizing signals, adjusting the voltage or the current of magnetic field control coils in accordance with the convergence error correction data. The system performs separate and independent convergence operations according to each region between the points of a horizontal and vertical reference pattern of a screen by generating separate and independent interpolation data according to each region between the correction points of the horizontal and vertical reference pattern of the screen and the adjusting the voltage or current of the magnetic coils in accordance with the interpolation data.
The system includes a method for storing a number of convergence error correction data corresponding to intersections of a screen, applying the convergence error correction data to respective convergence coils when the corresponding intersection is scanned, and applying the interpolation data when the corresponding area is scanned.
The system includes a method for generating a plurality of convergence error correction data that is independent of each other and independently feeding each of the convergence error correction data to convergence coils when each horizontal synchronization signal corresponding to each of the convergence error correction data starts.
The digital dynamic convergence error control system includes a convergence error detection device that recognizes intersections of a screen pattern displayed on a screen of a display device, detecting any amount of convergence errors corresponding to respective intersections; main control means generating correction data in response to respective convergence errors, interpolation data being generated using said correction data from adjacent intersections; and a digital dynamic convergence error control device that receives said correction data and said interpolation data from said main control means, said correction data and said interpolation data being stored in a memory, each of said correction data and said interpolation data being converted to voltage or current in response to respective horizontal synchronizing signals selected from an image signal and that independently and separately the said voltage or said current is supplied to a magnetic field control coil only during a corresponding period of respective horizontal synchronizing signals.
The digital dynamic convergence error control device of the system is integrated into a single chip with a monolithic structure.
The intersections of the screen pattern correspond to respective correction data and are formed by horizontal lines and vertical lines.
The interpolation data is generated in an area located between said adjacent intersections of said screen pattern, said area corresponding to horizontal synchronizing signals of said image signal present between said adjacent intersections of said screen pattern, said intersections of said screen pattern screen pattern are formed by horizontal lines and vertical lines.
The digital dynamic convergence error control device of the system comprises a controller that receives said correction data and said interpolation data and control command signals from said main control means, generating addresses corresponding to each of said correction data and said interpolation data, said interpolation data correction data and said interpolation data are stored in respective addresses of said memory and an address bus and a data bus are controlled to read out said correction data as well as said interpolation data from respective addresses of said memory; a reference clock generator that generates clock signals in response to a clock control signal input from said controller; an address generator that generates an interrupt signal and set-up signals for calculating said interpolation data according to an area between adjacent intersections in response to horizontal and vertical synchronization signals selected from said image signal, wherein control signals are generated from said controller and said clock signals are generated from said reference clock generator; an internal memory that stores said correction data and interpolation data entered at said controller; and an output section which converts said correction data and said interpolation data to said voltage and current in response to outgoing control signals generated from said controller as well as a conversion control signal generated from said address generator and wherein said voltage and said current are applied to said magnetic field control coils for generating magnetic fields with more than two poles.
The control signals of the controller are provided with a skip number, a first partial ratio, a throughput number and a second partial ratio, a first computer clock number and a main clock signal sent to said reference clock generator.
The setup signals from the address generator include an NCNT signal, a horizontal address, a vertical address, a horizontal control signal and a vertical control signal.
The system comprises a non-volatile external memory located outside said digital dynamic convergence error correction device coupled to said controller, in which said correction data and said interpolation data are stored, which said correction data and which said interpolation data stored in the said non-volatile memory is sent to said internal memory in response to a request signal from said controller.
The controller of the digital dynamic convergence error control device in the system generates the control signals by counting the number of clock signals generated from said reference clock generator during a period of a horizontal synchronization signal of said image signal in response to said clock control signal of said controller, said digital dynamic convergence error control device address generator comprising: a first counter and a first comparator generating an NCNT signal as one of the setup signals in response to said number of said clock signals counted during said period of the said horizontal synchronization signal, wherein a first interrupt signal is generated whenever there is a difference between the NCNT and a reference; a first divider that receives a skip number and a first divider ratio, which generates a horizontal control signal as one of said setup signals after dividing by said first dividing ratio of a remaining portion of said horizontal synchronization signal remaining after skipping said horizontal synchronization signal with a number of clock signals corresponding to the transfer number; a second counter that generates horizontal address signals by counting the horizontal control signal generated from said first divider; a second divider that receives a transit number and a second dividing ratio and generates a vertical control signal after dividing by said dividing ratio of a remaining portion of said vertical synchronization signal remaining after passing through a number of horizontal synchronizing signals corresponding to the transit number during said vertical synchronizing signal ; a third counter that generates a vertical address signal by counting the vertical control signal generated from the second divider; a fourth counter that generates a count value by counting the number of clock pulses of the horizontal synchronization signal during a vertical synchronization signal period; and a second comparator receiving said count value generated from the fourth counter, a second interrupt signal being output whenever a difference between the count value and a second reference is present by counting the number of clock pulses in each vertical synchronization signal, only when the first comparator generates said first interrupt signal.
The output section of the digital dynamic convergence error control device in the system comprises a number of digital-to-analog converters, each converting to an analog signal, said correction data and said interpolation data corresponding to respective magnetic field correction coils generating magnetic fields with more than two poles, which magnetic fields correspond to respective vertical and horizontal axes of said field correction coils; and a plurality of correction and interpolation units coupled to the respective said digital-to-analog converters and receiving said correction data and said interpolation data from said internal memory, sending said correction data and said interpolation data to corresponding digital -to-analog converters to control respective magnetic field control coils indicated by each coil address generated from said address generator with corresponding correction data and corresponding interpolation data.
The digital dynamic convergence error control device of the system comprises a first memory which stores and outputs said correction data in response to said horizontal and vertical address; a second memory that stores and outputs the interpolation data in response to said horizontal and vertical address; a counter for receiving vertical and horizontal synchronization signals from said address generator and each line number of said interpolation data from said second memory, each line number being counted of said horizontal synchronization signals existing during the vertical control signal by skipping said line number of said horizontal synchronization signals corresponding to said interpolation data; a multiplier for outputting a multiplied output signal by multiplying a counted signal from said counter with said interpolation data transmitted from said second controller in response to a release signal generated in accordance with said line number from said counter interpolation data from said second memory; a code bit discriminator for receiving and recognizing said interpolation data from said second memory, which outputs an operating signal depending on the status of said interpolation data and an adder unit and a subtraction unit for receiving said correction data from said first memory, and said interpolation data from said second memory, which adds and subtracks said multiplied output signal from said multiplier in response to said operating signal from said code bit discriminator.
The digital dynamic convergence error control device comprises a non-volatile external memory that stores correction data and interpolation data for correcting convergence errors corresponding to intersections of a screen pattern; a controller that receives said correction data and said interpolation data from said non-volatile external memory via a data bus and an address bus and generates control signals for progress to a convergence error correction and interpolation process for each portion of said screen pattern; a reference clock generator that generates clock signals in response to a clock control signal input from said controller; an address generator that generates an interrupt signal and setup signals for calculating said interpolation data corresponding to an area between adjacent intersections in response to horizontal and vertical synchronization signals selected from said image signal, control signals generated from said controller and said clock signals generated from said reference clock generator; an internal memory that stores said correction data and said interpolation data being input to said controller and an output section that converts said correction data and said interpolation data to said voltage and said current in response to outgoing control signals generated from said controller controller and a conversion control signal generated from said address generator and supplying said voltage and current to said magnetic field control coils for generating magnetic fields with more than two poles.
The digital dynamic convergence error control device is made from a single semiconductor chip in a monolithic structure other than the non-volatile external memory.
The intersections of the screen pattern correspond to respective correction data and are formed by horizontal lines and vertical lines.
The interpolation data is generated in an area located between the adjacent intersections of said screen pattern, said area corresponds to horizontal synchronization signals of said image signal present between said neighboring intersections of said screen pattern and said intersections of said screen pattern are formed by horizontal lines and vertical lines.
The control signals from the controller include a skip number, a first sub ratio, a transit number and a second sub ratio, a first comparator clock number and a main clock signal sent to said reference clock generator.
The setup signals from the address generator include an NCNT signal, a horizontal address, a vertical address, a horizontal control signal and a vertical control signal.
The controller generates the control signals by counting the number of clock signals generated by said reference clock generator during a period of a horizontal synchronization signal of said image signal in response to said clock control signal from said controller, which address generator of said digital dynamic convergence error control device comprises: a first counter and a first comparator that generates an NCNT signal as one of the setup signals in response to said number of said clock signals counted during said period of said horizontal synchronization signal, a first interrupt signal being generated when a difference is present between the NCNT and a reference; a first divider that receives a skip number and generates a first division ratio and a horizontal control signal as one of said setup signals after dividing by said first division ratio of a remaining portion of said horizontal synchronization signal that remained after skipping said horizontal synchronization signal with a number of clock signals corresponding to the transfer number; a second counter that generates a horizontal address signal by counting the horizontal control signal generated by said first divider; a second divider that receives a transit number and generates a second dividing ratio and a vertical control signal after dividing by said second dividing ratio of a remaining portion of said vertical synchronization signal remaining after passing a plurality of horizontal synchronizing signals corresponding to the transit number during said vertical synchronization number; a third counter that generates a vertical address signal by counting the vertical control signal generated by said second divider; a fourth counter that generates a count value by counting the number of clock pulses of the horizontal synchronization signal during a vertical synchronization signal period and a second comparator that receives said count value generated by said fourth counter and outputs a second interrupt signal each time a ver - there is a gap between the count value and a second reference by counting the number of clock pulses in each vertical synchronization signal, only when said first comparator generates said first interrupt signal.
The output section of the digital dynamic convergence error control device comprises a number of digital-to-analog converters that convert to said analog signal the said correction data and said interpolation data corresponding to respective magnetic field correction coils generating magnetic fields with more than two poles corresponding to respective vertical and horizontal axes of said magnetic field correction coils and a number of correction and interpolation sections coupled to said digital-to-analog converters, respectively, which receive said correction data and said interpolation data from said internal memory, said correction data and send said interpolation data to a corresponding digital-to-analog converter to control respective magnetic field control coils designated by each coil address that is generated from said address generator with corresponding correction data and said interpolation data.
The digital dynamic convergence error control device comprises a correction and interpolation section, comprising: a first memory that stores and outputs the correction data in response to said horizontal and vertical addresses; a second memory that stores and outputs said interpolation data in response to said horizontal and vertical address; a counter for receiving vertical and horizontal synchronization signals from said address generator and each line number of said interpolation data from said second memory, counting each line number of said horizontal synchronization signals existing during the vertical control signal by skipping said line number from said horizontal synchronization signals corresponding to said interpolation data; a multiplier for outputting a multiplied output signal by multiplying a counted signal from said counter with said interpolation data sent from said second controller in response to a release signal generated in accordance with said line number of said interpolation signal data from said second memory; a code bit discriminator for receiving and recognizing said interpolation data from said second memory, outputting an processing signal depending on the status of said interpolation data and an adder and a subtractor for receiving said correction data from the first memory and said interpolation data from said second memory, which adds said multiplied output signal from said multiplier and subtracks said multiplied output signal from said multiplier in response to said processing signal from said code bit discriminator.
A deflection yoke with a digital dynamic convergence error correction device comprises a coil separator with a neck portion coupled to a CRT; a horizontal deflection coil and a vertical deflection coil present on said coil separator; a plurality of magnetic field control coils for generating magnetic fields with more than two poles; a non-volatile external memory that stores correction data and interpolation data for correcting convergence errors corresponding to intersections of a screen pattern; a controller that receives said correction data and said interpolation data from said non-volatile external memory via a data bus and an address bus, generating control signals for proceeding with a convergence error correction and interpolation process for each portion of said screen pattern; a reference clock generator that generates clock signals in response to a clock control signal input from said controller; an address generator that generates an interrupt signal and setup signals for calculating said interpolation data corresponding to an area between adjacent intersections in response to horizontal and vertical synchronization signals selected from said image signal, control signals generated from said controller and said clock signals generated from said reference clock generator; an internal memory storing said correction data and said interpolation data being input to said controller and an output section converting said correction data as well as said interpolation data in said voltage and said current in response to output control signals generated from said controller and a conversion control signal generated from said address generator and applying said voltage and current to said magnetic field control coils for generating magnetic fields with more than two poles.
The deflection yoke provided with a digital dynamic convergence error correction device is characterized in that said controller, said reference clock generator, said address generator, said internal memory and said output section are all integrated in a single semiconductor chip with a monolithic structure.
The deflection yoke provided with a digital dynamic convergence error correction device is characterized in that said intersections of said screen pattern correspond to respective correction data and are formed by horizontal lines and vertical lines.
In the deflection yoke provided with a digital dynamic convergence error correction device, the feature is present that said interpolation data is generated in an area located between said adjacent intersections of said screen pattern, which area corresponds to horizontal synchronizing signals of said image signal present between said image signal adjacent intersections of said screen pattern, said intersections of said screen pattern being formed by horizontal and vertical lines.
The control signals of said controller include a skip number, a first sub ratio, a throughput number and a second sub ratio, a first computer clock number and a main clock signal that is sent to said reference clock generator.
The address generator setup signals include an NCNT signal, a horizontal address, a vertical address, a horizontal control signal, and a vertical control signal.
The controller of the deflection yoke provided with the digital dynamic convergence error correction device generates the control signals by counting the number of clock signals generated by said reference clock generator during a period of a horizontal synchronizing signal of said image signal in response to said clock control signal from said controller , said address generator of said digital dynamic convergence error control device comprising: a first counter and a first comparator generating an NCNT signal as one of the setup signals in response to said number of said clock signals counted during said period of said horizontal syn synchronization signal, and which generate a first interrupt signal whenever there is a difference between the NCNT and a reference; a first divider that receives a skip number and generates a first dividing ratio, a horizontal control signal as one of said setup signals after dividing by said first dividing ratio of a remaining portion of said horizontal synchronizing signal remaining after skipping said horizontal synchronizing signal with a number of clock signals corresponding to the transfer number; a second counter that generates a horizontal address signal by counting the horizontal control signal generated by said first divider; a second divider that receives a transit number and generates a second dividing ratio and a vertical control signal after dividing by said second dividing ratio of a remaining portion of said vertical synchronizing signal that remains after passing a plurality of horizontal synchronizing signals corresponding to the passing number during said vertical synchronization signal; a third counter that generates a vertical address signal by counting the vertical control signal generated by said second divider; a fourth counter that generates a count value by counting the number of clock pulses of the horizontal synchronization signal during a vertical synchronization signal period and a second comparator that receives said count value generated by said fourth counter, outputs a second interrupt signal whenever a difference is present is between the count value and a second reference by counting the number of clock pulses in each vertical synchronization signal, only when said first comparator generates said first interrupt signal.
The output section of the deflection yoke is characterized in that the output section comprises: a number of digital-to-analog converters which convert to each analog signal the said correction data and the said interpolation data corresponding to respective magnetic field correction coils generating magnetic fields with more than two poles corresponding to respective vertical and horizontal axes of said magnetic field correction coils and a number of correction and interpolation sections coupled to said digital-to-analog converters respectively, receiving said correction data and said interpolation data from said internal memory, send said correction data and said interpolation data to a corresponding digital-to-analog converter to control respective magnetic field control coils indicated by each coil address generated by said address generator with corresponding correction data and the aforementioned interpolation data.
The deflection yoke with the digital dynamic convergent error correction device comprises a correction and interpolation section with a first memory which stores and outputs the correction data in response to said horizontal and vertical address; a second memory that stores and outputs said interpolation data in response to said horizontal and vertical address; a counter for receiving vertical and horizontal synchronization signals from said address generator and each line number of said interpolation data from said second memory, counting each line number of said horizontal synchronization signals existing during the vertical control signal by skipping with said line number of the said horizontal synchronization signals corresponding to said interpolation data; a multiplier for outputting a multiplied output signal by multiplying a counted signal from said counter with said interpolation data sent from said second controller in response to a release signal generated in accordance with said line number of said interpolation data from said second memory ; a code bit discriminator for receiving and recognizing said interpolation data from said second memory, outputting an processing signal depending on the status of said interpolation data and an adder and a subtractor for receiving said correction data from said first memory and said interpolation data from said second memory adding and subtracting said multiplied output signal from said multiplier in response to said processing signal from said code bit discriminator.
A display device with a digital dynamic convergence error correction device comprises a deflection yoke that deflects electron beams emitted from an electron gun of a CRT; a plurality of magnetic field control coils for generating magnetic fields with more than two poles; a non-volatile external memory that stores correction data and interpolation data for correcting convergence errors corresponding to intersections of a screen pattern; a controller that receives said correction data and said interpolation data from said non-volatile external memory via a data bus and an address bus, generating control signals for proceeding a convergence error correction and interpolation process for each portion of said screen pattern; a reference clock generator that generates clock signals in response to a clock control signal input from said controller; an address generator that generates an interrupt signal and setup signals for calculating said interpolation data according to an area between adjacent intersections in response to horizontal and vertical synchronization signals selected from said image signal, control signals generated from said controller and said clock signals generated from said reference clock generator; an internal memory that stores said correction data and said interpolation data being input from said controller and an output section that converts said correction data and said interpolation data to said voltage and said current in response to outgoing control signals generated from said controller as well a conversion control signal generated from said address generator and said voltage and applying said current to said magnetic field control coils for generating magnetic fields with more than two poles.
The display device is characterized in that said controller, said reference clock generator, said internal memory and said output section are all integrated in a single semiconductor chip with a monolithic structure.
The display device is characterized in that said intersections of said screen pattern correspond to respective correction data and are formed by horizontal lines and vertical lines.
The display device is characterized in that said interpolation data is generated in an area located between said adjacent intersections of said screen pattern, said area corresponding to horizontal synchronizing signals of said image signal located between said adjacent intersections of said screen pattern, wherein said intersections of said screen pattern are formed by horizontal lines and vertical lines, said convergence error correction data corresponding to respective intersections of said screen pattern formed by horizontal and vertical lines.
The controller of the display device provided with a digital dynamic convergence error correction device generates the control signals by counting the number of clock signals generated by the reference clock generator during a period of a horizontal synchronization signal of the image signal in response to the clock control signal of the controller. The address generator of the digital dynamic convergence error control device comprises a first counter and a first comparator that generate an NCNT signal as one of the setup signals in response to said number of said clock signals counted during said period of said horizontal synchronizing signal, a generating a first interrupt signal every time there is a difference between the NCNT and a reference; a first divider that receives a skip number and a first divide ratio, generating a horizontal control signal as one of said setup signals after dividing by said first dividing ratio of a remaining portion of said horizontal synchronizing signal remaining after skipping said horizontal synchronizing signal by a plurality of clock signals corresponding to said throughput number; a second counter that generates a horizontal address signal by counting the horizontal control signal generated from said first divider; a second divider that receives a transit number and generates a second dividing ratio and a vertical control signal after dividing by said second dividing ratio of a remaining portion of said vertical synchronizing signal remaining after passing a plurality of horizontal synchronizing signals corresponding to the passing number during the said vertical synchronizing signal; a third counter that generates a vertical address signal by counting the vertical control signal generated from said second divider; a fourth counter that generates a count value by counting the number of clock pulses of the horizontal synchronization signal during a vertical synchronization signal period and a second comparator that receives said count value generated from the fourth counter, executing a second interrupt signal each time a there is a difference between the count value and a second reference by counting the number of clock pulses in each vertical synchronization signal, only when said first comparator generates said first interrupt signal.
The output section of the display device provided with a digital dynamic convergence error correction device comprises a number of digital-to-analog converters which in each analog signal convert said correction data and said interpolation data corresponding to respective magnetic field correction coils generating magnetic fields with more than two poles corresponding to the respective vertical and horizontal axes of said magnetic field correction coils and a plurality of correction and interpolation sections coupled to respective said digital-to-analog converters, receiving said correction data and said interpolation data from said internal memory, said correction data and sending said interpolation data to a corresponding digital-to-analog converter to control respective magnetic field control coils indicated by each coil address is generated by said address generator with corresponding correction data and said interpolation data.
The display device provided with a digital dynamic convergence error correction device comprises a correction interpolation section with a first memory which stores and outputs the correction data in response to said horizontal and vertical address; a second memory that stores and outputs the interpolation data in response to said horizontal and vertical address; a counter for receiving vertical and horizontal synchronization signals from said address generator and each line number of said interpolation data from said second memory, counting each line number of said horizontal synchronization signals existing during the vertical control signal by skipping said line number from said address horizontal synchronization signals corresponding to said interpolation data; a multiplier for outputting a multiplied output signal by multiplying a counted signal from said counter with said interpolation data sent from said second controller in response to a release signal generated in accordance with said line number of said interpolation data from said second memory ; a code bit discriminator for receiving and recognizing said interpolation data from said second memory, wherein an processing signal is output depending on the status of said interpolation data and an adder and a subtractor for receiving said correction data from said first memory and the said first memory and the said interpolation data from said second memory adding and subtracting said multiplied output signal from said multiplier in response to said processing signal from said code bit discriminator.
An apparatus for generating a convergence reference signal for correcting convergence errors in an image displayed on a CRT screen by controlling a number of magnetic field control coils for generating magnetic fields with more than two poles corresponding to a horizontal or vertical axis includes a controller that generates control signals, including a skip number, a transit number, a first partial ratio, a second partial ratio and clock pulses; a first counter and a first comparator generating a counted number by counting the number of clock pulses during a period of a horizontal synchronizing signal, generating a first interrupt signal whenever there is a difference between said counted number and a reference number; a first divider receiving a skip number as well as said first divide ratio, said number of said clock pulses corresponding to the skip number subtracting from the period of the horizontal synchronizing signal, dividing a remaining period of the subtracted horizontal synchronizing signal by the first dividing ratio and a generating horizontal control signal; a second counter that generates a horizontal address signal by counting said horizontal control signal generated from said first divider, a second divider receiving said second divide ratio as well as said transit number representing a number of horizontal synchronization signals being eliminated, the number of horizontal synchronization signals subtrahering corresponding to the transit number of a total number of horizontal synchronization signals during a period of said vertical synchronization signal, dividing a remaining number of said horizontal synchronization signals of said vertical synchronization signal by said second sub-ratio and generating a vertical control signal; a third counter that generates a vertical address signal by counting said vertical control signal; a fourth counter generating a count value by counting the number of clock pulses of the horizontal synchronization signal during the period of a vertical synchronization signal and a second comparator receiving the count value generated from said fourth counter and outputting a second interrupt signal, whenever there is a difference between the count value and a reference value in each vertical synchronization signal, only when said first comparator generates said first interrupt signal.
In the apparatus for generating a convergence reference signal for correcting convergence errors in the image displayed on the CRT screen, the convergence reference signal for the correction of convergence errors in an image displayed on a screen of a CRT is generated in response to said control signals by reading correction data and interpolation data stored in a memory coupled to said device in accordance with the number of said clock signals counted during said period of said horizontal synchronizing signal.
In a digital dynamic convergence error correction device provided with an address generator for generating a convergence error correction point address for correcting convergence errors of an image displayed on a screen of a CRT and an interpolation device for performing a convergence error and interpolation process by controlling respective magnetic field control track - corresponding to vertical and horizontal axes, comprises a correction and interpolation device, a first memory which stores and outputs the correction data in response to said horizontal and vertical address; a second memory that stores and outputs the interpolation data in response to said horizontal and vertical address; a counter for receiving vertical and horizontal synchronization signals from said address generator and each line number of said interpolation data from said second memory, counting each line number of said horizontal synchronization signals that exist during the vertical control signal by skipping said line number from the said horizontal synchronization signals corresponding to said interpolation data; a multiplier for outputting a multiplied output signal by multiplying a counted signal from said counter with said interpolation data sent from said controller in response to a release signal generated in accordance with said line number of said interpolation data from said second memory; a code bit discriminator for receiving and recognizing said interpolation data from said second memory, outputting an processing signal depending on the status of said interpolation data and an adder and subtractor for receiving said correction data from said first memory and said interpolation data from said second memory adding and subtracting said multiplied output signal from said multiplier in response to said processing signal from said code bit discriminator.
The interpolation device of the digital dynamic convergence error correction device is characterized in that an area for correcting said convergence error in accordance with said correction data output from said first memory corresponds to respective correction points of said screen which are indicated by respective convergent error correction reference point addresses.
The interpolation device of the digital dynamic convergence error correction device is characterized in that an area to be interpolated in accordance with said interpolation data output from said second memory corresponds to said horizontal synchronization signals present between correction points indicated by respective adjacent convergence error correction reference point addresses .
BRIEF DESCRIPTION OF THE INVENTION
A more complete understanding of the present invention and many of its advantages will be readily apparent when they are better understood by reference to the following detailed description in conjunction with the accompanying drawings in which the same reference numerals designate the same or similar parts, wherein : FIG. 1 is a schematic drawing showing a conventional convergence correction data generator, FIG. 2 is a diagram of the convergence correction data generator of FIG. 1, FIG. 3 is a reference screen pattern adapted for use with the convergence correction data generator of FIG. 2, FIG. 4 to 9 are diagrams showing two-pole magnetic fields, four-pole magnetic fields, six-pole magnetic fields, established in a structure provided with eight coils adapted for use in a dynamic convergence correction device, FIG. 10 is a schematic diagram showing a system adapted for use with a digital dynamic convergence control method, FIG. 11 is a reference screen pattern adapted for use with the digital dynamic convergence control method, FIG. 12 is a block diagram showing a digital dynamic convergence control system at a CRT display device, FIG. 13 is a block diagram of an address generator of FIG. 12, FIG. 14 is a block diagram of a correction and interpolation circuit of FIG. 12, FIG. 15 is a schematic diagram useful for explaining both the reference screen pattern and all definitions of the expressions of the digital dynamic convergence control system, FIG. 16 are waveforms showing a horizontal correction operation, FIG. 17 is a diagram showing a vertical interpolation, FIG. 18 is a diagram showing pixels for interpolation in the reference screen pattern, FIG. 19 is a diagram showing intervals for interpolation in the reference screen pattern, FIG. 20 is a schematic diagram of a magnetic field control yoke device, FIG. 21 is a diagram showing coils for generating two-pole magnetic fields with a horizontal axis in the magnetic field control yoke of FIG. 20, FIG. 22 is a diagram showing coils for generating two-pole magnetic fields with a vertical axis in the magnetic field control yoke of FIG.
20, FIG. 23 is a diagram showing coils for generating four-pole magnetic fields with a horizontal axis in the magnetic field control yoke of FIG. 20, FIG. 24 is a diagram showing coils for generating four-pole magnetic fields with a vertical axis in the magnetic field control yoke of FIG.
20, FIG. 25 is a diagram showing coils for generating six-pole magnetic fields with a horizontal axis in the magnetic field control yoke of FIG. 20, FIG. 26 is a diagram showing coils for generating six-pole magnetic fields with a vertical axis in the magnetic field control yoke of FIG. 20, FIG. 27 is a schematic diagram showing a magnetic field control yoke device coupled to the digital convergence control system constructed in accordance with the principles of the present invention and FIG. 28 is a schematic diagram showing a deflection yoke and a CRT of a display device coupled to the digital convergence control system constructed in accordance with the principles of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
In the conventional convergence error controller, predetermined types of current waves are supplied for the entire display in response to the convergence error using magnetic field correction coils to generate two-pole, four-pole, and six-pole magnetic fields as shown in each of FIG. 4 to 9.
However, in the present invention, when each divided area of the display is independently compensated by an independent convergence error, the respective areas present in each field of a display having 60 fields per second, the areas are corrected independently with respective independent and variable convergence errors .
Since a number of independent convergence errors correspond to respective areas in a single field of the display, the respective areas are corrected only with the corresponding convergence errors that do not affect each other. Thus, a very high resolution for the image quality is achieved by the independent convergence error correction signals only for the respective areas.
In the conventional methods, although the convergence error is corrected over the entire display, there is still a convergence error in a specific area of the display. When a convergence error of one area of the display is corrected by a convergent outcorrection signal, the other area of the display where the convergence error has already been corrected displays a different convergence error since the convergence error correction signal affects the other area. In addition, when a convergence error correction signal is applied to the deflection yoke for correction of the convergence error in a specific area, a different convergence error is input at a different area since the convergence error affects another area that does not have the same magnitude of the convergence error while the specific convergence error of the specific area could be corrected by the convergence error correction signal.
While it is disadvantageous that not the entire area of the entire display can be corrected with the conventional method, the present invention in contrast provides respective independent convergence error correction signals corresponding to each of the specific areas in the field of the display without adjacent others areas. These improvement properties make the convergence error correction system in a single chipset lightweight and of small dimensions.
FIG. 4 to 9 show the state of a deflection force exerted on each of the RGB electron beams when a correction current is applied to the magnetic field correction coils for generating two-pole magnetic fields, four-pole magnetic fields and six-pole magnetic fields poles in accordance with convergence error correction signals.
FIG. 4 shows horizontal two-pole magnetic field correction coils and deflection directions of each of the RGB electron beams in response to a convergence error correction current applied to the magnetic field correction coils for generating two-pole magnetic fields. All RGB electron beams move in the same horizontal direction.
FIG. 5 shows vertical two-pole magnetic field correction coils and deflection directions of each of the RGB electron beams in response to convergence error correction currents applied to magnetic field correction coils for generating two-pole magnetic fields. All RGB electron beams move in the same vertical direction.
FIG. 6 shows horizontal quadrupole magnetic field correction coils and deflection directions of each of the RGB electron beams in response to a convergence error correction current applied to magnetic field correction coils for generating four-pole magnetic fields. The R and B electron beams move in the opposite horizontal direction.
FIG. 7 shows vertically quadrupole magnet field correction coils and deflection directions of each of the RGB electron beams in response to a convergence error correction current applied to magnetic field correction coils for generating four-pole magnetic fields. The R and B electron beams move in opposite vertical directions.
FIG. 8 shows horizontal six-pole magnetic field correction coils and deflection directions of each of the RGB electron beams in response to a convergence error correction current applied to the magnetic field correction coils for generating six-pole magnetic fields. The R and B electron beams move in the same horizontal direction.
FIG. 9 shows six-pole vertical magnetic field correction coils and deflection directions of each of the RGB electron beams in response to a convergence error correction current applied to magnetic field correction coils for generating six-pole magnetic fields. The R and B electron beams move in the same vertical direction.
Since the magnitude of the deflection force for the RGB electron beams varies depending on the convergence error correction current, it is necessary to control the convergence error correction current for correcting the respective convergence errors. As described above, a combination of magnetic field correction coils for generating two-pole, four-pole, and six-pole magnetic fields in a horizontal direction and a vertical direction is commonly referred to as a convergence yoke adapted for use with magnetic field adjusting means.
FIG. 10 is a schematic diagram showing a convergence error detection and correction system for use in a digital dynamic convergence control method. A convergence detection device detects a reference screen pattern displayed on a screen of a CRT, with magnetic field control coils mounted on a deflection yoke DY. Main control means provided with a control computer are coupled to the convergence detection device and a digital dynamic convergence error correction device. The CRT and the deflection yoke DY are coupled to the digital convergence error correction device. A setup control signal is input at the control computer.
The digital dynamic convergence error control device stores convergence error correction data corresponding to each intersection (correction point) of the screen pattern in respective predetermined addresses of a memory, produces read addresses of the memory for reading out the convergence error correction data corresponding to the intersections (correction points) when each of said correction points is scanned in response to horizontal and vertical synchronization signals obtained from an image signal to be displayed on a CRT display device, independently reads out each of the convergence error correction data from the memory in response to the respective readout address and controls the magnetic field control coils after the convergence error correction data has been amplified and converted into a control voltage signal or a control current signal.
The convergence error correction data corresponding to respective correction points of the screen pattern as shown in FIG. 11 represent the control voltage signal or the control current signal supplied to each of the two-pole, four-pole or six-pole magnetic field control coils as shown in FIG. 10, the convergence error correction data is sent to the digital dynamic convergence error controller after being calculated from the magnitude of the convergence error that occurred at the correction points of the screen pattern detected by the convergence error detection device using control logic and a beam tracking analysis method.
The predetermined addresses and the read addresses for storing convergence error correction data in the memory and for reading out the convergence error correction data from the memory comprise a combination of a vertical position number of each correction point, a horizontal position number of each correction point, a specific number for the correction point indicating the magnetic field control coils receiving the control voltage signal or control current signal corresponding to each correction point, with these characteristics, the convergence error of each correction point is independently adjusted and controlled without affecting other correction points of the screen pattern.
The correction points MCP11 to MCP55 are independently controlled as shown in FIG. 11, using the above features established in accordance with the principles of the present invention. With respect to each of the correction points, all control voltage signals or control current signals supplied to each of the two-pole, four-pole and six-pole magnetic field control coils as shown in FIG. 4 to 6 controlled and adjusted to independently correct the convergence error according to the respective correction points. The convergence error of the RGB electron beams are independently controlled to a certain state by using operating principles of the magnetic field control coils. The operating principles of the magnetic field control coils are substantially the same as those of a convergence purity magnet mounted on a neck portion of the deflection yoke.
The digital dynamic convergence error control system comprises the convergence error detection device, main control means, as well as a digital dynamic convergence error correction device, which together form a closed loop. The closed loop repeats operations of. the aforementioned convergence error detection process until desired convergence error correction data corresponding to the correction points is obtained during the repetitive convergence error detection process. When the desired convergence error correction is obtained, all convergence error data corresponding to the respective correction points are stored in an EEPROM of the memory present in a controller of the digital dynamic convergence error correction device. After the correction data is stored in the EEPROM, the digital dynamic convergence error correction device present within the broken line of FIG. 10 is operated independently of the convergence error detection device and the main control means.
After the convergence error correction process is completed, a CRT structure is combined with the digital dynamic convergence error correction device, the magnetic field control coils, the deflection yoke, and the CRT display device from the digital dynamic convergence error control system. When power is supplied to the CRT structure, a controller of the digital dynamic convergence error controller reads the convergence error correction data from the EEPROM and performs a convergence error correction process in an open loop.
Since the convergence error correction data obtained from the repeated convergence error detection process is determined in an external control computer located outside of the digital dynamic convergence error control device, an internal microprocessor of the digital dynamic convergence error control device performs a number of operations, such as a data transmission process and a data storage process, other than a convergence error detection process and a convergence error correction signal determining process. The digital dynamic convergence error control device thus need not have any additional memory or additional processor. Since the digital dynamic convergence error control device only needs to have output functions of the convergence error correction data without performing the convergence error detection process and the convergence error correction signal determination process for calculating the convergence error correction data in real time and in accordance with a scanning period of the intersections of the screen pattern, implementation of the digital dynamic convergence error controller.
A more detailed structure and operation of the digital dynamic convergence error controller are shown in FIG. 12.
FIG. 12 is a block diagram showing a digital dynamic convergence error control device in a CRT display device. All functional modules except reference number 12 can be integrated on a chip with a monolithic structure. The device comprises a controller with a microprocessor, a memory with an EEPROM 12 and a set of RAM memories 13A, 13B, a read-out address generator with a phase-locked loop (PLL) 14 and an address generator 16, as well as an output section provided of a correction and interpolation unit 17 and a digital-to-analog converter 18.
The digital dynamic convergence error correction device includes a FIRM mode, a HOME mode and a TEST mode in response to a control command signal.
The microprocessor 11 of the controller of the digital dynamic convergence error correction device makes a determination in response to the control command signal whether an operational mode of the digital dynamic convergence error correction device consists of the FIRM mode with the closed loop for producing the convergence error correction data and interpolation data, the HOME mode with the open loop for outputting the convergence error correction and interpolation data stored in a memory or EEPROM 12, and the TEST mode.
In accordance with the determination, when the closed mode is selected, the microprocessor 11 of the controller generates a number of storage addresses for storing the convergence error correction data and the control command signals sent from an external device, the address generator 16 controls the transmission of the stored addresses to the address ports of the RAM 13A, 13B in response to a termination signal from the control command signals and stores the convergence error correction data by transmitting the convergence error correction data and a write release signal to the data ports of the RAM 13A, 13B. When the end signal of the control command signals is transmitted after the convergence error correction process is completed, the convergence error correction data stored in RAM 13A, 13b is stored in EEPROM 12 coupled to the external device.
When the open loop is selected, the microprocessor 11 reads the convergence error correction data stored in EEPROM 12 and stores it in RAM 13A, 13B. After the convergence error correction data is stored in RAM 13A, 13B, the microprocessor 11 generates control signals to enable the address generator 16 to output addresses and send the addresses to the address ports of RAM 13A, 13B and generates a readout signal (RE) to RAM 13A, 13B to read out the convergence error correction data from RAM 13A, 13B.
A first RAM 13A and a second RAM 13B store different types of data. The convergence error correction data is stored in the first RAM 13A while the interpolation data is stored in the second RAM 13B.
The interpolation data is obtained from a difference between the convergence error correction data corresponding to a first correction point formed by a first point of the intersections of the screen pattern and the convergence error correction data corresponding to a second correction point that is adjacent to the first correction point and located below the first correction point. The difference is divided by the number of horizontal scan lines located between the two adjacent correction points to produce the interpolation data used to increase and reduce the convergence error correction data, depending on the number of horizontal scan lines within a vertical period of the display.
When the end signal of the control command signal is sent to the microprocessor 11, the microprocessor 11 controls the address generator 16 to send the memory addresses outputted from the microprocessor 11 to the address ports of RAM 13A, 13B via an address bus and to transmit the convergence error correction data to store in RAM 13A and the interpolation data in RAM 13B. When the final signal is input, the convergence error correction data and the interpolation data are stored in the external memory EEPROM 12.
When the open loop is selected, the microprocessor 11 stores the convergence error correction data and the interpolation data in RAM 13A, 13B respectively sent from EEPROM 12. After the convergence error correction data and the interpolation data are stored in RAM 13A, 13B, respectively, control signals are generated to the address generator 16 to send read addresses to address ports of RAM 13A, 13B and the RE signal is generated to read the RAM 13A, 13B.
The address generator 16 outputs the readout addresses for the convergence error correction data and the interpolation data stored in RAM 13A, 13B in accordance with a start point of the horizontal scan lines corresponding to each of the correction points in response to horizontal and vertical synchronization signals.
The correction and interpolation unit 17 generates all convergence error correction data and all interpolation data corresponding to the line number of the horizontal scan lines present in a vertical scan period using the convergence error correction data and the interpolation data output from RAM 13A, 13B, respectively, in response on the readout addresses of the address generator 16.
As described above, the integrated digital dynamic convergence error controller includes the three modes: the FIRM mode, the HOME mode, the TEST mode.
In FIRM mode, the microprocessor 11 receives from an external control computer via an RS-232C cable or an I2C communication bus the control command signals and the data used for the convergence error correction process and the interpolation process from an external computer via an RS-232C cable or I2C bus, in response to the control command signals, stores the received data in RAM 13A, 13B or in EEPROM 12 coupled to the microprocessor 11 via an I2C communication bus or any external communication means and stores the data in RAM 13A, 13B to those read from the EEPROM 12. In response to the current mode of the CRT structure, the control signals are generated via the I2C communication bus and, in response to the control signal, the microprocessor 11 transmits the control signals to the address generator 16 and an interpolation control signal to the correction and interpolation unit 17.
In the HOME mode, the microprocessor 11 reads through the I2C communication bus the convergence error correction data and interpolation data stored in EEPROM 12, stores the convergence error correction data and the interpolation data in RAM 13A, 13B, transmits the control signals to the address generator 16 and the interpolation control signals to the correction and interpolation unit 17 and then receives an interrupt signal generated by the address generator 16 and the CRT structure. In response to the interrupt signal sent from the address generator 16 and the CRT structure, the control signals and the interpolation control signals can be changed.
In the TEST mode, in accordance with a program for the TEST, the address generator 16, the RAM 113A, 113B, the correction and interpolation unit 17 and the PLL 14 are tested.
Regardless of the above three modes, the PLL 14 outputs clock signals in the range of 20 MHz and 280 MHz in response to a frequency selection signal generated by the microprocessor 11.
After one of the three modes is selected, the predetermined operation corresponding to the selected mode is performed. When the operation of the selected mode is terminated, the predetermined addresses and control signals are generated by the address generator 16 and the correction and interpolation data read from the memory at the respective addresses are sent to the correction and interpolation unit 17 which outputs a new set of data to the digital-to-analog converter 18 according to a new screen size to DAC in response to the control signals.
The address generator 16 and the correction and interpolation unit 17 are described in detail below and are shown in FIG. 13 and 14.
FIG. 13 is a block diagram of the address generator 16 for counting the number of clock pulses FVCO generated by the PLL 14 in response to a PLL control signal from the controller 11 during a period of a horizontal synchronization signal and for generating a counted number and the controller 11 generates the control signals in accordance with the counted number of the address generator 16.
The address generator 16 comprises a first counter C1 and a first comparator C01 which outputs the NCNT signal in response to a counted number of clock pulses during the period of the horizontal synchronization signal, comparing the NCNT signal with previously stored NCNT signals in each period of the generating a horizontal synchronizing signal and a first interrupt signal when there is a difference between the NCNT signal and the previously stored NCNT signal, a first divider D1 receiving a transfer number and a first division ratio from the controller 11 and generating horizontal control signals after division by the first sub-ratio of a remaining period of the horizontal synchronizing signal that remains after a number of clock pulses FVCO corresponding to the transfer number have been eliminated from the horizontal synchronizing signal, a second counter C2 generating horizontal address signals by counting the horizontal control signals generated by the first divider D1, a second divider D2 receiving a transit number and generating a second division ratio 2 and a vertical control signal after division by the second division ratio 2 of a remaining period of the vertical synchronization signal remaining after elimination of a number of horizontal scan lines corresponding to the transit number from the horizontal synchronization signals present within a period of the vertical synchronization signal, wherein a third counter C3 generates a vertical address signal by counting the vertical control signal generated by the second divider D2, a fourth counter C4 generating a second counted number by counting the number of the horizontal synchronization signals presented during a vertical synchronization signal period and a second comparator C02 receives the second counted number generated by the fourth counter ~ C4 and outputs a second interrupt signal when there is a difference between the second counted number and a pre-stored second counted number in each period of the vertical synchronization signal, only when the first interrupt signal is generated by the first comparator C01.
The correction and interpolation unit 17 shown in FIG. 14 includes a RAM 1-1 18A that stores and outputs the convergence error correction data in response to the horizontal and vertical address signals, a RAM 2-1 18B that stores and outputs the interpolation data in response to the horizontal and vertical address signals, a fifth counter 18C which after skipping the number of lines of the horizontal synchronization signals according to the interpolation data counts the number of the horizontal synchronization signals that exist during the remaining period of the vertical control signal in response to the number of lines of the horizontal synchronization signals according to the interpolation data from RAM 2-1 18B and in response to the vertical control signal and the horizontal synchronizing signals input from the address generator 16, wherein a multiplier 18D outputs a multiplied output signal by multiplying the third counted numbers of the fifth counter 18C with the interpolation data also transmitted from the controller 11 in response to a release signal generated in accordance with the number of lines of the horizontal synchronization signals according to the interpolation data from the RAM 2-1 18B, a code bit discriminator 18G outputting an operation signal in accordance with the correction data and the interpolation data generated from RAM 2-1 18B and wherein an adder 18E and a subtractor 18F add the correction data and interpolation data received from RAM 1-1 18A, RAM 2-1, 18B and the multiplied outgoing data from the multiplier 18D and subtracking, respectively, of the operating signal of the code bit discriminator in response to the correction data and interpolation data from RAM 1-1 18A, RAM 2-1 18B.
The correction and interpolation unit 17 may comprise a multiplexer (MUX) 18H for selectively selecting one of the outputs from the adder 18E and the subtracter 18F, as well as a buffer 181 for temporarily storing and delaying one of the output signals output by the MUX 18H.
The clock signals FVCO generated by the PLL 14 in response to the control signals from the controller 11 are input to the address generator 16. The clock signals FVCO do not vary regardless of the variation of the vertical synchronization signal and the horizontal synchronization signal in terms of the period and the number of the vertical synchronizing signals and the horizontal synchronizing signals. When the number of clock signals FVCO is counted during the period of the horizontal synchronizing signal and is sent to the microprocessor 11, the microprocessor 11 generates the control signals including the skip number, the pass number, a first division ratio, a second division ratio and the first comparator clock number. These control signals can be determined in advance.
A first divider D1 receives the skip number and the first divide ratio, subtracts the number of clock pulses FVCO corresponding to the skip number of the period of the horizontal synchronization signal, divides a remaining period of the subtracted horizontal synchronization signal by the first division ratio and generates horizontal control signals. A second counter C2 generates horizontal address signals by counting the horizontal control signals.
A second divider D2 receives the transit number and the second division ratio, subtracts a number of scanning lines of the horizontal synchronization signals corresponding to the passage number of the period of the vertical synchronization signal, divides a remaining period of the sub-subtracted vertical synchronization signal by the second division ratio and generates vertical control signals. A third counter C3 generates vertical address signals by counting the vertical control signals.
The first counter C1 generates the NCNT signal by counting the number of clock signals FVCO during the horizontal synchronizing signal period and the first comparator C01 receives the NCNT signal and generates a difference signal when there is a difference of at least one clock pulse between the received NCNT signal and the previously stored NCNT signal by comparing the received NCNT signal with the previously stored NCNT signal. With the first comparator C01, the first interrupt signal is generated in response to the difference caused by the variation of the horizontal synchronizing signal.
The fourth counter C4 counts the number of clock signals corresponding to the number of horizontal synchronizing signals generated during the vertical synchronizing signal period and generates the second counted number to the second comparator C2. The second comparator C2 compares the second counted number and a previously stored second counted number when each vertical synchronizing signal is input and generates the second interrupt signal in response to the first interrupt signal when a difference between the second counted number and a previously stored second counted number is present in each period of the vertical synchronization signal.
Properties and sources of each signal are described as follows.
The horizontal synchronization signal, the vertical synchronization signal and a display mode conversion signal are generated by a TV device with a CRT structure that communicates with the external computer via the serial communication means RS-232C.
The external control command signal is an input signal to select one of the modes in the convergence error correction device that is integrated into a single chip. The control signals containing the first division ratio, the skip number, the second division ratio, the transit number, the first comparator clock number and the MUX control signal are sent from the microprocessor 11 to the address generator 16 and can be input by a manufacturer of TV equipment .
A PLL control signal input from the microprocessor 11 to the PLL 14 consists of a predetermined frequency number and the interpolation control signal is input from the microprocessor 11 to the correction and interpolation unit 17 to change and edit the interpolation data.
As in FIG. 13, the address generator 16 generates the NCNT signal, the horizontal address signals, the vertical address signals, the horizontal control signals, the vertical control signals, and the first and second interrupt signals in response to the control signals output from the microprocessor 11 including the transfer number, the first partial ratio, the transit number, the second partial ratio, the first comparator clock number, the FVCO signal, the vertical synchronizing signal and the horizontal synchronizing signal. FIG. 15 shows the characteristics of all control signals generated from the address generator 16 and the microprocessor 11 in conjunction with the CRT structure display.
The outgoing frequency generated by the PLL 14, the FVCO signal, is determined by the frequency control signal sent from the microprocessor 11 and the outgoing frequency of the FVCO signal is input at the input ports of the first counter C1 and the first divider respectively Dl.
The first divider D1 subtracts the transmit number of the number of clock pulses of the FVCO signal corresponding to period of the horizontal synchronization signal, generates a remaining period of the horizontal synchronization signal, divides the remaining period of the horizontal synchronization signal by the first division ratio D1 to the horizontal generate the control signal and generate the horizontal address signals by counting the horizontal control signal in the second counter C2.
The second divider D2 subtracts the pass number of the number of horizontal synchronization signals during the period of the synchronization signal, generates a remaining period of the vertical synchronization signal, divides the remaining period of the vertical synchronization signal by the second sub-ratio D2 and generates the vertical control signal around the vertical address signal to be generated by counting the vertical control signal in the third counter C3.
The first counter C1, see FIG. 16, generates the NCNT signal by counting the number of the FVCO signals during each period of the horizontal synchronizing signal. The first comparator C01 receives the NCNT signal and makes a determination whether at least one clock pulse difference is present between the received NCNT signal and a pre-stored NCNT signal and generates the first interrupt signal in response to the determination that the received NCNT signal is different of the previously stored NCNT signal. The first interrupt signal indicating that the frequency of the horizontal synchronizing signal has been changed is sent to the microprocessor 11.
After the frequency of the horizontal synchronization signal is changed, the fourth counter C4 counts the number of horizontal synchronization signals that are input during the period of the vertical synchronization signal and outputs the second counted number to the second counter C2. The second interrupt signal indicating that the resolution of the display has been changed is sent to the microprocessor 11 when the second counted number differs from a pre-stored number in the second comparator CO2.
The second interrupt signal is generated in response to the determination of the resolution change of the display such as the total number of the horizontal synchronization signals presented during the period of the vertical synchronization signal after the first interrupt signal is generated in response to the frequency change of the display horizontal synchronization signal.
Once the first interrupt signal has been generated in response to the frequency change of the horizontal synchronization signal, the microprocessor 11 calculates a second pass number, a third sub-ratio and a third comparator clock number all of which are used for the changed horizontal synchronization signal in accordance with the magnitude of the frequency change of the horizontal synchronizing signal and transmits to the address generator 16 the second transfer number, the third division ratio and the third comparator clock number. Once the second interrupt signal has been generated in response to the resolution ratio of the display, the microprocessor 11 calculates a second pass number and a fourth sub-ratio used for the changed horizontal synchronization signals in accordance with the number of the horizontal synchronization signals and transmits them to the address generator 16 the second transit number and the fourth division ratio.
In FIG. 15, all terminology of the control signals is explained in connection with the screen pattern and the screen. The first partial ratio and the second partial ratio represent the distance between the horizontal addresses and between the vertical addresses, respectively, which all form the intersections of the screen pattern shown in FIG. 15 and the first partial ratio is shown along the horizontal direction while the second partial ratio is shown along the vertical direction.
The skip number represents a vertical skip area of the display formed by a first difference between a first signal area formed by the horizontal synchronizing signals and a first displayed area displayed on a physical screen of the CRT structure. The transit number represents a horizontal kickback area of the display which is formed by a second difference between a second signal area formed by the vertical synchronizing signal and a second displayed area displayed on the physical screen of the CRT structure.
As described above, when the first interrupt signal is generated in response to the frequency change of the horizontal synchronization signal, the microprocessor 11 calculates, according to the magnitude of the frequency change of the horizontal synchronization signal, the second pass number, the third division ratio, the fourth comparator clock number, which are sent to the address generator 16. When the second interrupt signal in response to the change in resolution caused by the change in the number of the horizontal synchronizing signals presented during the vertical synchronizing signal period is generated, the microprocessor 11 generates the second transit number and the fourth division ratio sent to the address generator 16.
Whenever the frequency change or the resolution change of the horizontal synchronization signal occurs, modified addresses are generated to accurately perform the correction and interpolation process at the predetermined positions with the changed horizontal and vertical synchronization signals. v
The address generator 16 generates the horizontal control signals, the vertical control signals, the horizontal address signals and the vertical address signals in response to the first control signals or to the second control signals.
The first RAM 13A stores the correction data corresponding to the convergence errors of the respective intersections (correction points) of the screen pattern while the second RAM 13B stores the interpolation data of the convergence errors corresponding to each region between two adjacent intersections. Although all areas between the adjacent intersections do not have the correction data, the area may have the interpolation data to correct the convergence errors in the areas located between the intersections.
The correction data and the interpolation data stored in the respective first and second RAM 13A, 13B are output in response to the respective addresses generated by the address generator 16. Since the correction data and the interpolation data are independently assigned to respective addresses. The corresponding correction data or the corresponding interpolation data are output independently and separately to the respective addresses. The interpolation data includes code bits, the line number, and the interpolation size.
A third counter 18C counts the number of horizontal synchronization signals located within the period of the vertical synchronization signal, the number of the horizontal synchronization signals only corresponding to the interpolation data. The counted number sent to the multiplier 18D is multiplied by the interpolation size of the interpolation data to generate the multiplied magnitude to the adder 18E and the subtractor 18F which are operated in accordance with the code bits of the interpolation data. The multiplied size is added to or subtracted from the correction data.
The areas of the horizontal and vertical kickback periods, which are not displayed on the physical screen, can be controlled in response to the horizontal and vertical control signals set by the user or by the manufacturer via the MUX 18H set by the user. When each period of the horizontal synchronization signal starts, the correction data corresponding to a first period of a first horizontal synchronization signal is output before the first synchronization signal is generated. The predetermined horizontal and vertical control signals input by the user are output in the period determined by the transit number. The correction data and the interpolation data for correcting the convergence errors are output after each period of the horizontal synchronization signals corresponding to the skip number.
The number of code bits of the interpolation data stored in the second RAM 18B varies in response to the resolution change of the display. If the resolution is changed because the number of horizontal synchronization signals is changed, then the number of the horizontal synchronization signals located between the adjacent correction points and the interpolation size of the interpolation data fed to the interpolation process should be adjusted. Since the interpolation data varies according to each display, the number of code bits for forming the line number and the interpolation size of the interpolation data is changed.
When the second interrupt is generated in response to the resolution change, the microprocessor 11 generates the recalculated second control signals in accordance with the changed resolution. The number of the code bits and the calculation of the counters, the multiplier, the adder and the subtractor are changed in response to the recalculated second control signals.
In the magnetic field control yoke, the four pairs of magnetic field control coils made of double windings or triple windings are located around the yoke on opposite sides as shown in FIG. 20. The connection pins indicate 2V, 2H, 4V, 4H, 6V, 6H and ground respectively.
When the digital dynamic convergence error controller operates, respective operations of the magnetic field control yoke in response to the correction data and the interpolation data are shown in FIGs. 21 to 26. The magnetic field control yoke acts as two-pole magnetic field control coils, four-pole magnetic field control coils, or six-pole magnetic field control coils.
The outgoing signals from the output section 18 of FIG. 12 are sent to the terminal pins of FIG. 20 via respective amplifiers (not shown). The horizontal two-pole magnetic field control coils are shown in FIG. 21 while the vertical two-pole magnetic field control coils are shown in FIG. 22 and the horizontal quadrupole magnetic field control coils are shown in FIG. 23 while the vertical quadrupole magnetic field control coils are shown in FIG. 24. The horizontal six pole magnet field control coils are shown in FIG. 25 while the vertical six-pole magnet field control coils are shown in FIG. 26.
FIG. 25 is a diagram showing the digital dynamic convergence error correction device connected to the magnetic field control yoke while FIG. 26 is a diagram showing the digital dynamic convergence error correction device connected to the magnetic field control yoke and the CER structure of the display device.
The digital dynamic convergence error correction device is made as a separate printed circuit board or is integrated into a common printed circuit board in a monolithic structure. FIG. 27 and 28 show an example of the digital dynamic convergence error correction device mounted on the display device in various ways.
As described above, the convergence error is corrected by providing the digital dynamic convergence error correction device that corrects the convergence error that occurs at the correction control points formed by the intersections of the screen pattern and by applying the control current or the control voltage to the magnetic field control coils to generate two-pole magnetic fields, four-pole magnetic fields or six-pole magnetic fields. The convergence errors incurred at each correction control point are therefore corrected over entire portions of the display. High definition quality that accomplishes this convergence error correction can be implemented in an HDTV that is currently available on the current market.
Although the preferred embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is described. in the claims and their equivalents.

权利要求:
Claims (49)
[1]
A digital dynamic convergence error control system, characterized by: a convergence error detection device that recognizes intersections of a screen pattern displayed on a screen of a display device, wherein any amount of convergence errors corresponding to respective intersections is detected; main control means generating correction data in response to respective convergence errors, interpolation data being generated using said correction data from adjacent intersections; and a digital dynamic convergence error control device that receives said correction data and said interpolation data from said main control means, said correction data and said interpolation data being stored in a memory, each of said correction data and said interpolation polarity data is converted to voltage or current in response to respective horizontal synchronizing signals selected from an image signal and that independently and separately said voltage or current is supplied to a magnetic field control coil only during a corresponding period of respective horizontal synchronizing signals.
[2]
A system according to claim 1, characterized in that said digital dynamic convergence error control device is integrated in a single chip with a monolithic structure.
[3]
The system of claim 1, wherein said intersections of said screen pattern correspond to respective correction data and are formed by horizontal lines and vertical lines.
[4]
A system according to claim 1, characterized in that said interpolation data is generated in an area located between said adjacent intersections of said screen pattern, said area corresponding to horizontal synchronizing signals of said image signal present between said adjacent intersections of said screen pattern, said intersections of said screen pattern being formed by horizontal lines and vertical lines.
[5]
A system according to claim 1, characterized in that said digital dynamic convergence error control device comprises: a controller receiving said correction data and said interpolation data and the control command signals from said main control means, generating addresses corresponding to each of said correction data and said interpolation data, said correction data and said interpolation data are stored in respective addresses of said memory and an address bus and a data bus are controlled to read out said correction data as well as said interpolation data from respective addresses of said memory; a reference clock generator that generates clock signals in response to a clock control signal input from said controller; an address generator that generates an interrupt signal and set-up signals for calculating said interpolation data according to an area between adjacent intersections in response to horizontal and vertical synchronization signals selected from said image signal, wherein control signals are generated from said controller and said clock signals are generated from said reference clock generator; an internal memory that stores said correction data and interpolation data entered at said controller; and an output section which converts said correction data and said interpolation data to said voltage and current in response to outgoing control signals generated from said controller as well as a conversion control signal generated from said address generator and wherein said voltage and said current are applied to said magnetic field control coils for generating magnetic fields with more than two poles.
[6]
A system according to claim 5, characterized in that said control signals and said controller are provided with a skip number, a first division ratio, a transit number and a second division ratio, a first comparator clock number and a main clock signal sent to said reference clock generator.
[7]
A system according to claim 5, characterized in that said setup signals from said controller include an NCNT signal, a horizontal address, a vertical address, a horizontal control signal and a vertical control signal.
[8]
A system according to claim 5, characterized in that the system further comprises: a non-volatile external memory located outside said digital dynamic convergence error correction device coupled to said controller, wherein said correction data and said interpolation data are stored, said correction data and said interpolation data stored in said non-volatile memory are sent to said internal memory in response to a request signal from said controller.
[9]
A system according to claim 5, characterized in that the digital dynamic convergence error control device comprising said controller generates said control signals by counting the number of said clock signals generated from said reference clock generator during a period of a horizontal synchronizing signal of said image signal in response to said clock control signal from said controller, wherein said address generator of the digital dynamic convergence error control device comprises -. a first counter and a first comparator generating an NCNT signal as one of the setup signals in response to said number of said clock signals counted during said period of said horizontal synchronization signal, a first interrupt signal being generated each time a there is a difference between the NCNT and a reference; a first divider that receives a skip number and a first divider ratio, which generates a horizontal control signal as one of said setup signals after dividing by said first dividing ratio of a remaining portion of said horizontal synchronization signal remaining after skipping the said horizontal synchronizing signal with a number of clock signals corresponding to the transfer number; a second counter that generates horizontal address signals by counting the horizontal control signal generated from said first divider; a second divider that receives a transit number and a second dividing ratio and generates a vertical control signal after dividing by said dividing ratio of a remaining portion of said vertical synchronization signal remaining after passing through a number of horizontal synchronizing signals corresponding to the transit number during said vertical synchronizing signal ; a third counter that generates a vertical address signal by counting the vertical control signal generated from the second divider; a fourth counter that generates a count value by counting the number of clock pulses of the horizontal synchronization signal during a vertical synchronization signal period; and a second comparator receiving said count value generated from the fourth counter, a second interrupt signal being output whenever a difference between the count value and a second reference is present by counting the number of clock pulses in each vertical synchronization signal, only when the first comparator generates said first interrupt signal.
[10]
System according to claim 5, characterized in that said digital dynamic convergence error control device comprises: a number of digital-to-analog converters, each of which converts to an analog signal, said correction data and said interpolation data corresponding to respective magnetic field correction coils that generate magnetic fields with more than two poles, which magnetic fields correspond to respective vertical and horizontal axes of said field correction coils; and a plurality of correction and interpolation units coupled to the respective said digital-to-analog converters and receiving said correction data and said interpolation data from said internal memory, sending said correction data and said interpolation data to corresponding di -gital-to-analog converters to control respective magnetic field control coils indicated by each coil address generated from said address generator with corresponding correction data and corresponding interpolation data.
[11]
A system according to claim 5, characterized in that said digital dynamic convergence error control device comprises: a first memory which stores and outputs said correction data in response to said horizontal and vertical address; a second memory that stores and outputs the interpolation data in response to said horizontal and vertical address; a counter for receiving vertical and horizontal synchronization signals from said address generator and each line number of said interpolation data from said second memory, each line number being counted of said horizontal synchronization signals existing during the vertical control signal by skipping said line number of said horizontal synchronization signals corresponding to said interpolation data; a multiplier for outputting a multiplied output signal by multiplying a counted signal from said counter with said interpolation data transmitted from said second controller in response to a release signal generated in accordance with said line number from said interpolation data from said second memory; a code bit discriminator for receiving and recognizing said interpolation data from said second memory, which outputs an operating signal depending on the status of said interpolation data and an adder unit and a subtraction unit for receiving said correction data from said first memory, and said interpolation data from said second memory, which adds and subtracks said multiplied output signal from said multiplier in response to said operating signal from said code bit discriminator.
[12]
A digital dynamic convergence error control device, characterized in that it comprises: a non-volatile external memory that stores correction data and interpolation data for correcting convergence errors corresponding to intersections of a screen pattern; a controller that receives said correction data and said interpolation data from said non-volatile external memory via a data bus and an address bus and generates control signals for progress to a convergence error correction and interpolation process for each portion of said screen pattern, a reference clock generator generates clock signals in response to a clock control signal input from said controller; an address generator that generates an interrupt signal and setup signals for calculating said interpolation data corresponding to an area between adjacent intersections in response to horizontal and vertical synchronization signals selected from said image signal, control signals generated from said controller and said clock signals generated from said reference clock generator; an internal memory storing said correction data and said interpolation data being input to said controller and an output section converting said correction data and said interpolation data to said voltage and said current in response to outgoing control signals generated from said controller and a conversion control signal generated from said address generator and supplying said voltage and current to said magnetic field control coils for generating magnetic fields with more than two poles.
[13]
An apparatus according to claim 12, characterized in that said digital dynamic convergence error control device is made from a single semiconductor chip in a monolithic structure, apart from said non-volatile external memory.
[14]
Apparatus according to claim 12, characterized in that said intersections of said screen pattern correspond to respective correction data and are formed by horizontal lines and vertical lines.
[15]
Apparatus according to claim 12, characterized in that said interpolation data is generated in an area located between the adjacent intersections of said screen pattern, said area corresponding to horizontal synchronizing signals of said image signal present between said neighboring intersections of said screen pattern and said intersections of said screen pattern are formed by horizontal lines and vertical lines.
[16]
An apparatus according to claim 12, characterized in that said control signals from said controller comprise a skip number, a first sub ratio, a throughput number and a second sub ratio, a first comparator clock number and a main clock signal sent to said reference clock generator.
[17]
Apparatus according to claim 12, characterized in that said setup signals from said address generator include an NCNT signal, a horizontal address, a vertical address, a horizontal control signal and a vertical control signal.
[18]
An apparatus according to claim 12, characterized in that said controller generates said control signals by counting the number of said clock signals generated by said reference clock generator during a period of a horizontal synchronizing signal of said image signal in response to said clock control signal from said controller, which address generator of said digital dynamic convergence error control device comprises: a first counter and a first comparator that generates an NCNT signal as one of the setup signals in response to said number of said clock signals counted during said period of said horizontal synchronization signal, a first interrupt signal being generated when there is a difference between the NCNT and a reference; a first divider that receives a skip number and generates a first division ratio and a horizontal control signal as one of said setup signals after dividing by said first division ratio of a remaining portion of said horizontal synchronization signal that remained after skipping said horizontal synchronization signal with a number of clock signals corresponding to the transfer number; a second counter that generates a horizontal address signal by counting the horizontal control signal generated by said first divider; a second divider that receives a transit number and generates a second dividing ratio and a vertical control signal after dividing by said second dividing ratio of a remaining portion of said vertical synchronization signal remaining after passing a plurality of horizontal synchronizing signals corresponding to the transit number during said vertical synchronization number; a third counter that generates a vertical address signal by counting the vertical control signal generated by said second divider; a fourth counter that generates a count value by counting the number of clock pulses of the horizontal synchronization signal during a vertical synchronization signal period and a second comparator that receives said count value generated by said fourth counter and outputs a second interrupt signal whenever a difference occurs is present between the count value and a second reference by counting the number of clock pulses in each vertical synchronization signal, only when said first comparator generates said first interrupt signal.
[19]
An apparatus according to claim 12, characterized in that the output section comprises: a plurality of digital-to-analog converters that convert to said analog signal said correction data and said interpolation data corresponding to respective magnetic field correction coils generating magnetic fields with more than two poles corresponding to respective vertical and horizontal axes of said magnetic field correction coils and a plurality of correction and interpolation sections coupled to said digital-to-analog converters, respectively, receiving said correction data and said interpolation data from said internal send memory, said correction data and said interpolation data to a corresponding digital-to-analog converter to control respective magnetic field control coils designated by each coil address generated from said address generator with corresponding correction data and said interpolation data.
[20]
An apparatus according to claim 12, characterized in that the apparatus is further provided with a correction and interpolation section, comprising: a first memory which stores and outputs the correction data in response to said horizontal and vertical addresses; a second memory that stores and outputs said interpolation data in response to said horizontal and vertical address; a counter for receiving vertical and horizontal synchronization signals from said address generator and each line number of said interpolation data from said second memory, counting each line number of said horizontal synchronization signals existing during the vertical control signal by skipping said line number from said horizontal synchronization signals corresponding to said interpolation data; a multiplier for outputting a multiplied output signal by multiplying a counted signal of said counter with said interpolation data transmitted from said second controller in response to a release signal generated in accordance with said line number of said interpolation data from said second memory; a code bit discriminator for receiving and recognizing said interpolation data from said second memory, outputting an processing signal depending on the status of said interpolation data and an adder and a subtractor for receiving said correction data from the first memory and said interpolation data from said second memory, which adds said multiplied output signal from said multiplier and subtracks said multiplied output signal from said multiplier in response to said processing signal from said code bit discriminator.
[21]
A deflection yoke with a digital dynamic convergent error correction device, characterized in that the deflection yoke comprises: a coil separator with a neck portion coupled to a CRT; a horizontal deflection coil and a vertical deflection coil present on said coil separator; a plurality of magnetic field control coils for generating magnetic fields with more than two poles; a non-volatile external memory that stores correction data and interpolation data for correcting convergence errors corresponding to intersections of a screen pattern; a controller that receives said correction data and said interpolation data from said non-volatile external memory via a data bus and an address bus, generating control signals for proceeding with a convergence error correction and interpolation process for each portion of said screen pattern; a reference clock generator that generates clock signals in response to a clock control signal input from said controller; an address generator that generates an interrupt signal and setup signals for calculating said interpolation data corresponding to an area between adjacent intersections in response to horizontal and vertical synchronization signals selected from said image signal, control signals generated from said controller and said clock signals generated from said reference clock generator; an internal memory storing said correction data and said interpolation data being input to said controller and an output section converting said correction data as well as said interpolation data in said voltage and said current in response to output control signals generated from said controller and a conversion control signal generated from said address generator and applying said voltage and current to said magnetic field control coils for generating magnetic fields with more than two poles.
[22]
The deflection yoke according to claim 21, characterized in that said controller, said reference clock generator, said address generator, said internal memory and said output section are all integrated in a single semiconductor chip with a monolithic structure.
[23]
The deflection yoke according to claim 21, characterized in that said intersections of said screen pattern correspond to respective correction data and are formed by horizontal lines and vertical lines.
[24]
The deflection yoke according to claim 21, characterized in that said interpolation data is generated in an area located between said adjacent intersections of said screen pattern, which area corresponds to horizontal synchronizing signals of said image signal present between said adjacent intersections of said screen pattern, said intersections of said screen pattern being formed by horizontal and vertical lines.
[25]
A deflection yoke according to claim 21, characterized in that said control signals from said controller comprise a skip number, a first sub ratio, a throughput number and a second sub ratio, a first comparator clock number and a main clock signal that is sent to said reference clock generator.
[26]
A deflection yoke according to claim 21, characterized in that said setup signals from said address generator comprise an NCNT signal, a horizontal address, a vertical address, a horizontal control signal and a vertical control signal.
[27]
A deflection yoke according to claim 21, characterized in that said controller generates said control signals by counting the number of clock signals generated by said reference clock generator during a period of a horizontal synchronizing signal of said image signal in response to said clock control signal of said controller comprising said address generator of said digital dynamic convergence error control device: a first counter and a first comparator generating an NCNT signal as one of the setup signals in response to said number of said clock signals counted during said period of said horizontal synchronizing signal, and which generate a first interrupt signal whenever there is a difference between the NCNT and a reference; a first divider that receives a skip number and generates a first dividing ratio, a horizontal control signal as one of said setup signals after dividing by said first dividing ratio of a remaining portion of said horizontal synchronizing signal remaining after skipping said horizontal synchronizing signal with a number of clock signals corresponding to the transfer number; a second counter that generates a horizontal address signal by counting the horizontal control signal generated by said first divider; a second divider that receives a transit number and generates a second dividing ratio and a vertical control signal after dividing by said second dividing ratio of a remaining portion of said vertical synchronization signal remaining after passing a plurality of horizontal synchronizing signals corresponding to the passing number during said vertical synchronization signal; a third counter that generates a vertical address signal by counting the vertical control signal generated by said second divider; a fourth counter that generates a count value by counting the number of clock pulses of the horizontal synchronization signal during a vertical synchronization signal period and a second comparator that receives said count value generated by said fourth counter, outputs a second interrupt signal whenever a difference is present is between the count value and a second reference by counting the number of clock pulses in each vertical synchronization signal, only when said first comparator generates said first interrupt signal.
[28]
The deflection yoke according to claim 21, characterized in that the output section comprises: a plurality of digital-to-analog converters which convert to each analog signal said correction data and said interpolation data corresponding to respective magnetic field correction coils generating magnetic fields with more then two poles corresponding to respective vertical and horizontal axes of said magnetic field correction coils and a plurality of correction and interpolation sections coupled to said digital-to-analog converters respectively, receiving said correction data and said interpolation data from said internal memory , send said correction data and said interpolation data to a corresponding digital-to-analog converter to control respective magnetic field control coils indicated by each coil address generated by said coil address generator with corresponding correction data and the aforementioned interpolation data.
[29]
A deflection yoke according to claim 21, characterized in that it further comprises a correction and interpolation section, comprising: a first memory storing and outputting the correction data in response to said horizontal and vertical address; a second memory that stores and outputs said interpolation data in response to said horizontal and vertical address; a counter for receiving vertical and horizontal synchronization signals from said address generator and each line number of said interpolation data from said second memory, counting each line number of said horizontal synchronization signals existing during the vertical control signal by skipping with said line number of the said horizontal synchronization signals corresponding to said interpolation data; a multiplier for outputting a multiplied output signal by multiplying a counted signal from said counter with said interpolation data sent from said second controller in response to a release signal generated in accordance with said line number of said interpolation data from said second memory ; a code bit discriminator for receiving and recognizing said interpolation data from said second memory, outputting an processing signal depending on the status of said interpolation data and an adder and a subtractor for receiving said correction data from said first memory and said interpolation data from said second memory adding and subtracting said multiplied output signal from said multiplier in response to said processing signal from said code bit discriminator.
[30]
30. A display device provided with a digital dynamic convergence error correction device; characterized in that the device comprises: a deflection yoke deflecting electron beams emitted from an electron gun of a CRT; a plurality of magnetic field control coils for generating magnetic fields with more than two poles; a non-volatile external memory that stores correction data and interpolation data for correcting convergence errors corresponding to intersections of a screen pattern; a controller that receives said correction data and said interpolation data from said non-volatile external memory via a data bus and an address bus, generating control signals for proceeding a convergence error correction and interpolation process for each portion of said screen pattern; a reference clock generator that generates clock signals in response to a clock control signal input from said controller; an address generator that generates an interrupt signal and setup signals for calculating said interpolation data according to an area between adjacent intersections in response to horizontal and vertical synchronization signals selected from said image signal, control signals generated from said controller and said clock signals generated from said reference clock generator; an internal memory that stores said correction data and said interpolation data being input from said controller and an output section that converts said correction data and said interpolation data to said voltage and said current in response to outgoing control signals generated from said controller as well a conversion control signal generated from said address generator and said voltage and applying said current to said magnetic field control coils for generating magnetic fields with more than two poles.
[31]
A display device according to claim 30, characterized in that said controller, said reference clock generator, said internal memory and said output section are all integrated in a single semiconductor chip with a monolithic structure.
[32]
32. The display device of claim 30, wherein: characterized in that said intersections of said screen pattern correspond to respective correction data and are formed by horizontal lines and vertical lines.
[33]
A display device according to claim 30, characterized in that said interpolation data is generated in an area located between said adjacent intersections of said screen pattern, said area corresponding to horizontal synchronization signals of said image signal which is located between said adjacent intersections of said screen pattern, said intersections of said screen pattern being formed by horizontal lines and vertical lines, said convergence error correction data corresponding to respective intersections of said screen pattern formed by horizontal and vertical lines.
[34]
34. A display device as claimed in Claim 30, characterized in that said control signals from said controller comprise a skip number, a first partial ratio, a transit number, as well as a second partial ratio, a first comparator clock number and a main clock signal which is sent to the said reference clock generator.
[35]
A display device according to claim 30, characterized in that said setup signals from said address generator comprise an NCNT signal, a horizontal address, a vertical address, a horizontal control signal and a vertical control signal.
[36]
A display device according to claim 30, characterized in that said controller generates said control signals by counting the number of said clock signals generated from said reference clock generator during a period of a horizontal synchronizing signal of said image signal in response to said clock control signal from said controller, which address generator of the digital dynamic convergence error control device comprises: a first counter and a first comparator generating an NCNT signal as one of the setup signals in response to said number of the said clock signals being counted during said period of said horizontal synchronizing signal, generating a first interrupt signal whenever there is a difference between the NCNT and a reference; a first divider that receives a skip number and a first divide ratio, generating a horizontal control signal as one of said setup signals after dividing by said first dividing ratio of a remaining portion of said horizontal synchronizing signal remaining after skipping said horizontal synchronizing signal by a plurality of clock signals corresponding to said throughput number; a second counter that generates a horizontal address signal by counting the horizontal control signal generated from said first divider; a second divider that receives a transit number and generates a second dividing ratio and a vertical control signal after dividing by said second dividing ratio of a remaining portion of said vertical synchronization signal remaining after passing a plurality of horizontal synchronizing signals corresponding to the transit number during said vertical synchronization signal; a third counter that generates a vertical address signal by counting the vertical control signal generated from said second divider; a fourth counter generating a count value by counting the number of clock pulses of the horizontal synchronization signal during a vertical synchronization signal period and a second comparator receiving said count value generated from the fourth counter, executing a second interrupt signal whenever a difference is present is between the count value and a second reference by counting the number of clock pulses in each vertical synchronization signal, only when said first comparator generates said first interrupt signal.
[37]
A display device according to claim 30, characterized in that said output section comprises: a number of digital-to-analog converters which convert said correction data into each analog signal and said interpolation data corresponding to respective magnetic field correction coils generating magnetic fields with more than two poles corresponding to the respective vertical and horizontal axes of said magnetic field correction coils and a plurality of correction and interpolation sections coupled to respective said digital-to-analog converters, receiving said correction data and said interpolation data from said internal memory sending said correction data and interpolation data to a corresponding digital-to-analog converter to control respective magnetic field control coils indicated by each coil address generated for said address generator with corresponding correction data and said interpolation data.
[38]
A display device according to claim 30, characterized in that the device further comprises a correction and interpolation section, comprising: a first memory storing and outputting the correction data in response to said horizontal and vertical address; a second memory that stores and outputs the interpolation data in response to said horizontal and vertical address; a counter for receiving vertical and horizontal synchronization signals from said address generator and each line number of said interpolation data from said second memory, counting each line number of said horizontal synchronization signals existing during the vertical control signal by skipping said line number from said address horizontal synchronization signals corresponding to said interpolation data; a multiplier for outputting a multiplied output signal by multiplying a counted signal from said counter with said interpolation data sent from said second controller in response to a release signal generated in accordance with said line number from said interpolation data from said second memory; a code bit discriminator for receiving and recognizing said interpolation data from said second memory, wherein an processing signal is output depending on the status of said interpolation data and an adder and a subtractor for receiving said correction data from said first memory and the said interpolation data from said second memory, adding said multiplied output signal from said multiplier and sub-tracking in response to said processing signal from said code bit discriminator. 3§t Apparatus for generating a convergence reference signal for correcting convergence errors in an image displayed on a CRT screen by controlling a number of magnetic field control coils for generating magnetic fields with more than two poles corresponding to one of the horizontal and vertical axes, characterized in that the apparatus comprises: a controller that generates control signals including a skip number, a transit number, a first partial ratio, a second partial ratio and clock pulses; a first counter and a first comparator generating a counted number by counting the number of clock pulses during a period of a horizontal synchronizing signal, generating a first interrupt signal whenever there is a difference between said counted number and a reference number; a first divider that receives a skip number and said first divide ratio, said number of said clock pulses corresponding to the skip number subtracting from the period of the horizontal synchronizing signal, dividing a remaining period of the sub-horizontal horizontal synchronizing signal by the first divider attitude and generating a horizontal control signal; a second counter that generates a horizontal address signal by counting said horizontal control signal generated from said first divider; a second divider receiving said second partial ratio as well as said continuation number representing a number of horizontal synchronization signals being eliminated, subtracting the number of horizontal synchronization signals corresponding to the continuation number of a total number of horizontal synchronization signals during a period of said vertical synchronization signal, dividing a remaining number of said horizontal synchronization signals of said vertical synchronization signal by said second division ratio and a vertical control signal; a third counter that generates a vertical address signal by counting said vertical control signal; a fourth counter which generates a count value by counting the number of clock pulses of the horizontal synchronization signal during the period of a vertical synchronization signal and a second comparator receiving the count value generated from said fourth counter and outputting a second interrupt signal, each time a difference is present between the count value and a reference value in each vertical synchronization signal, only when said first comparator generates said first interrupt signal.
[39]
An apparatus according to claim 39, characterized in that said convergence reference signal for correcting convergence errors in an image displayed on a screen of a CRT is generated in response to said control signals by reading out correction data and interpolation data which are stored in a memory coupled to said device in accordance with the number of said clock signals counted during said period of said horizontal synchronizing signal.
[40]
41. A correction and interpolation apparatus in a digital dynamic convergence error correction apparatus, characterized in that it comprises: an address generator for generating a convergence error correction point address for correcting convergence errors of an image displayed on a CRT screen; an interpolation apparatus for performing a convergence error correction and interpolation process by controlling respective magnetic field control coils corresponding to vertical and horizontal axes; a first memory that stores and outputs the correction data in response to said horizontal and vertical address; a second memory that stores and outputs the interpolation data in response to said horizontal and vertical address; a counter for receiving vertical and horizontal synchronization signals from said address generator and each line number of said interpolation data from said second memory, counting each line number of said horizontal synchronization signals that exist during the vertical control signal by skipping said line number from the said horizontal synchronization signals corresponding to said interpolation data; a multiplier for outputting a multiplied output signal by multiplying a counted signal from said counter with said interpolation data sent from said controller in response to a release signal generated in accordance with said line number of said interpolation data from said second memory; a code bit discriminator for receiving and recognizing said interpolation data from said second memory, outputting an processing signal depending on the status of said interpolation data and an adder and subtractor for receiving said correction data from said first memory and said interpolation data from said second memory adding and subtracting said multiplied output signal from said multiplier in response to said processing signal from said code bit discriminator.
[41]
An interpolation apparatus according to claim 41, characterized in that an area for correcting said convergence error in accordance with said correction data output from said first memory corresponds to respective correction points of said screen indicated by respective convergence error correction reference point addresses.
[42]
A display device according to claim 41, characterized in that an area to be interpolated in accordance with said interpolation data output from said second memory corresponds to said horizontal synchronization signals present between correction points indicated by respective adjacent convergent out correct reference point addresses.
[43]
44. A convergence error correction apparatus in a display device, characterized in that it comprises a memory which stores a number of independent and separate convergence error correction data signals corresponding to respective correction points within a period of a specific horizontal synchronizing signal.
[44]
45. Convergence error correction device in a display device, characterized in that it comprises a memory which stores a number of independent and separate convergence error correction data signals corresponding to respective correction points within each period of specific horizontal synchronizing signals, which memory stores a number of interpolation data signals corresponding to horizontal synchronization signals present between adjacent correction points.
[45]
46. Convergence error correction device in a display device, characterized in that it comprises a controller which independently and separately generates a number of independent and separate convergence error correction data signals corresponding to respective correction points of a screen pattern and independently and separately supplies each of said error correction data signals to magnetic field control coils when each correction point corresponding to respective convergence error correction data signals is scanned in a screen.
[46]
47. A convergence error correction device in a display device, characterized in that it comprises: a memory that stores a number of independent and separate convergence error correction data signals corresponding to respective correction points within each period of specific horizontal synchronization signals, which memory stores a number of interpolation data signals corresponding to horizontal synchronization signals located between adjacent correction points and a controller coupled to said memory, independently each of said convergence error correction data signals readout from said memory when the corresponding correction point is scanned in a screen.
[47]
A convergence error correction device in a display device, characterized in that it comprises a controller that generates first separate independent convergence error correction data corresponding to respective first pixels in a first screen with a first screen size in response to the number of first horizontal synchronizing signals in a first vertical synchronization signal, which controller generates first separate and independent interpolation data signals corresponding to a first area present between adjacent first pixels, which controller generates second separate independent convergence correction data corresponding to respective second pixels in a second screen with a second screen size in response to the number of the second horizontal synchronization signals in a second vertical synchronization signal, which controller generates second separate and independent interpolation data signals corresponding to a second area located between adjacent second pixels.
[48]
A process in a convergence error correction apparatus, characterized in that it comprises the steps of: storing a number of independent separate convergence error correction data signals corresponding to respective correction points within each period of specific horizontal synchronization signals; storing a number of interpolation data signals corresponding to horizontal synchronization signals located between adjacent correction points and independently and separately generating a number of independent and separate convergence error correction signals corresponding to respective correction points of a screen pattern and independently and separately supplying each of the convergence error correction data signals to magnetic field control coils when each correction point corresponding to respective convergence error correction data signals is scanned in a screen.
[49]
A process in a convergence error correction device, characterized in that it comprises the steps of: storing first separate and independent convergence error correction data corresponding to respective first pixels in a first screen with a first screen dimension in response to the number of first horizontal synchronization signals in a first vertical synchronization signal; storing first separate and independent interpolation data signals according to a first area located between adjacent first pixels; converting said first convergence error correction data signals and said first interpolation data signals into second separate and independent convergence correction data and second interpolation data signals according to respective second pixels in a second screen signal with a second screen size in response to the number of second horizontal synchronizing signals in a second vertical synchronization signal.

类似技术:

---

公开号 | 公开日 | 专利标题

---

EP0420568B1|1996-02-28|Digital convergence apparatus

---

JP2861333B2|1999-02-24|Image correction device

---

US5537159A|1996-07-16|Interpolation method and apparatus for improving registration adjustment in a projection television

---

JPH05176238A|1993-07-13|Image pickup device

---

JPH06141351A|1994-05-20|Signal generator

---

US4733296A|1988-03-22|Multi-tube color TV camera in which linear and non-linear components of a registration error due to chromatic aberration of a lens are corrected with corresponding deflection correction signals

---

US5497054A|1996-03-05|Automatic digital convergence correcting method and apparatus therefor

---

US7061551B2|2006-06-13|Convergence control apparatus and method for compensating for angular error of reference pattern

---

NL1019845A1|2003-05-27|Digital dynamic convergence control system in a display system.

---

US6437522B1|2002-08-20|Method for controlling digital dynamic convergence and system thereof

---

CA2277844A1|1998-07-23|Alignment of cathode ray tube video displays using a host computer processor

---

US6359648B1|2002-03-19|High-quality image input apparatus with motion compensation function

---

EP0439598B1|1996-11-27|Convergence control system

---

US5436677A|1995-07-25|Focus voltage control apparatus

---

KR20040013813A|2004-02-14|Multi synchronous and multi resolution interpolation method in digital dynamic convergence control system

---

US20020113910A1|2002-08-22|Apparatus and method for controlling convergence in projection television

---

JPH07105951B2|1995-11-13|Digital convergence device

---

JPH0750936B2|1995-05-31|Digital convergence device

---

JPH07143501A|1995-06-02|Convergence error detector

---

JP3475675B2|2003-12-08|Digital convergence device

---

KR100232600B1|1999-12-01|Convergence data generating device of projection image device

---

US20030025831A1|2003-02-06|Video converter board

---

JPH0583749A|1993-04-02|Uniformity correction device

---

JPH0738902A|1995-02-07|Picture correction circuit

---

EP0817505A2|1998-01-07|Digital convergence system

同族专利:

---

公开号 | 公开日

---

GB2382510A|2003-05-28|

---

FR2832893A1|2003-05-30|

---

CN1423480A|2003-06-11|

---

US20030098930A1|2003-05-29|

---

GB0201158D0|2002-03-06|

---

FR2832894A1|2003-05-30|

---

JP2003169342A|2003-06-13|

---

KR20030042514A|2003-06-02|

引用文献:

---

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

---

---

JPH0736623B2|1981-04-30|1995-04-19|株式会社日立製作所|In-line color picture tube device|

---

JPS61281791A|1985-06-07|1986-12-12|Sony Corp|Digital convergence device|

---

JP3035912B2|1988-10-14|2000-04-24|ソニー株式会社|Image display correction waveform data generator|

---

EP0600540B1|1992-11-30|1998-02-11|Koninklijke Philips Electronics N.V.|Colour diplay tube including a convergence correction device|

---

KR0130871B1|1994-03-21|1998-04-21|김광호|Digital conversions adjust method and equipment|

---

US5847777A|1994-05-11|1998-12-08|George; John Barrett|Right-edge differential error convergence correction|

---

US6252626B1|1994-06-13|2001-06-26|Image Processing Systems, Inc.|Test and alignment system for electronic display devices|

---

JPH0898221A|1994-09-22|1996-04-12|Sony Corp|Characteristic evaluating display pattern for display device and evaluating method using this pattern|

---

US5828167A|1995-07-24|1998-10-27|Hitachi, Ltd.|Color cathode ray tube with a dynamic convergence device and color display system employing same|

---

JPH0984059A|1995-09-13|1997-03-28|Sony Corp|Convergence measurement device|

---

JP2001069523A|1999-08-31|2001-03-16|Sony Corp|Convergence correction device and convergence correction method|

---

KR100393559B1|2000-09-30|2003-08-02|삼성전기주식회사|Control method for digital dynamic convergence and system for the same|US6992803B2|2001-05-08|2006-01-31|Koninklijke Philips Electronics N.V.|RGB primary color point identification system and method|

---

JP3761491B2|2002-05-10|2006-03-29|Ｎｅｃビューテクノロジー株式会社|Projection image distortion correction method, distortion correction program, and projection-type image display device|

---

US7170550B2|2003-07-03|2007-01-30|Sony Corporation|Television data management system|

---

US20050012820A1|2003-07-03|2005-01-20|Sony Corporation|Data management process for television assembly|

---

PL380170A1|2004-01-06|2007-01-08|Thomson Licensing|Magnetic field compensation apparatus for cathode ray tube|

---

KR102238741B1|2015-01-06|2021-04-12|삼성디스플레이 주식회사|Method of measuring light emitting status of display panel and method of compensating light emitting status of display panel|

法律状态:
2003-08-01| AD1A| A request for search or an international type search has been filed|

---

2009-12-01| RD2N| Patents in respect of which a decision has been taken or a report has been made (novelty report)|

---

2010-01-04| EDI| The registered patent application has been withdrawn|

优先权:

---

申请号 | 申请日 | 专利标题

---

KR1020010073180A|KR20030042514A|2001-11-23|2001-11-23|Digital Dynamic Convergence Control System of Display Device at CRT Type|

---

KR20010073180|2001-11-23|

---